1. Field of the Invention
The present invention generally relates to a method for fabricating a semiconductor device, and more specifically to a method for fabricating a semiconductor device wherein a gate is formed on a stepped Si epitaxial layer to increase an effective length of a gate channel, and an oxide film is only formed at the interface of the Si epitaxial layer and the semiconductor substrate where a bit line contact is to be formed, thereby improving a characteristic of a leakage current for a storage node junction.
2. Description of the Related Art
FIG. 1 is a layout illustrating a method for fabricating a semiconductor device, wherein reference numerals 1000a, 1, 2 and 3 denote a cell region, an active region, a first gate region and a second gate region, respectively. The first gate region 2 is overlapped the second gate region 3. A line width of the first gate region 2 is less than a width of the second gate region 3.
FIGS. 2a through 2f are cross-sectional views illustrating a method for fabricating a semiconductor device, wherein FIGS. 2a(i) through 2f(i) are cross-sectional views taken along the line I-I′ in FIG. 1, and FIGS. 2a(ii) through 2f(ii) are cross-sectional views in a core/peripheral circuit region 1000b. 
Referring to FIG. 2a, a stacked structure of a SiGe epitaxial layer (not shown), a first Si epitaxial layer (not shown), a first oxide film (not shown) and a first nitride film (not shown) is formed on a semiconductor substrate 10 having a cell region 1000a and a core/peripheral circuit region 1000b defined therein. Next, a first photoresist film (not shown) is deposited on the entire surface of the first nitride film (not shown) in the cell region 1000a and the core/peripheral circuit region 1000b. Thereafter, the first photoresist film (not shown) is exposed and developed to form a first photoresist film pattern (not shown) exposing the first gate region 2 of FIG. 1 and covering the entire core/peripheral circuit region 1000b. After that, the stacked structure is etched using the first photoresist film pattern as an etching mask to expose the semiconductor substrate 10 corresponding to the first gate region 2 and the entire core/peripheral circuit region 1000b. The first photoresist film pattern is then removed.
Referring FIG. 2b, a first nitride film pattern 19 and a first oxide film pattern 17 in the cell region 1000a are removed via a wet etching method. Next, a second Si expitaxial layer 25 is formed on the entire surface of the cell region 1000a and the core/peripheral circuit region 1000b. 
Referring to FIG. 2c, a second oxide film 30 and a second nitride film 35 are formed on the second Si epitaxial layer 25 in the cell region 1000a and the core/peripheral circuit region 1000b. Next, a second photoresist film (not shown) is deposited on the entire surface of the second nitride film 35. The second photoresist film is then exposed and developed to form a second photoresist film pattern (not shown) defining the active region 1 of FIG. 1 in the cell region 1000a, and also an active region in the core/peripheral circuit region 1000b. Thereafter, the second nitride film 35, the second oxide film 30, the second Si epitaxial layer 25, the first Si epitaxial layer pattern 15, the SiGe epitaxial layer pattern 13 and a given thickness of the semiconductor substrate 10 are etched using the second photoresist film pattern as an etching mask to form a trench 40 in the cell region 1000a and the core/peripheral circuit region 1000b. After that, the second photoresist film pattern (not shown) is removed. The SiGe epitaxial layer pattern 13 is then etched through a sidewall of the trench 40 via a wet etching method to form a space 27 under the first Si epitaxial layer pattern 15.
Referring to FIG. 2d, a gap-filling insulating film 45 is formed on the entire surface to fill up the space 27 and the trench 40 in the cell region 1000a and to fill up the trench 40 in the core/peripheral circuit region 1000b. Next, the gap-filling insulating film 45 is polished until the second nitride film 35 is exposed. The gap-filling insulating film 45 serves as a device isolation structure. Thereafter, a given thickness of the gap-filling insulating film 45 in the trench 40 is etched. The second nitride film 35 is then removed via a wet etching method. After that, a well implant process and a channel implant process are performed so as to adjust impurity concentrations in the cell region 1000a and the core/peripheral circuit region 1000b. 
Referring to FIG. 2e, the second oxide film 30 in the cell region 1000a and the core/peripheral circuit region 1000b is removed via a wet etching method to expose the second Si epitaxial layer 25. A gate oxide film 50 is then formed on the exposed second Si epitaxial layer 25. Next, gate conductive layers 60 and 70, and a hard mask insulating film 80 are formed on the gate oxide film 50 and the gap-filling insulating film 45 in the cell region 1000a and the core/peripheral circuit region 1000b. 
Referring to FIG. 2f, a third photoresist film (not shown) is deposited on the hard mask insulating film 80 in the cell region 1000a and the core/peripheral circuit region 1000b. Thereafter, the third photoresist film (not shown) is exposed and developed to form a third photoresist film pattern defining the second gate region 3 of FIG. 1 and a gate region (not shown) in the core/peripheral circuit region 1000b. Specifically, the third photoresist film pattern exposes a bit line contact region and storage node contact regions in the cell region 1000a and covers a region where a gate is to be formed in the core/peripheral circuit region 1000b. Next, the hard mask insulating film 80 and the gate conductive layers 70 and 60 are etched using the third photoresist film pattern as an etching mask to respectively form a gate 90 in the cell region 1000a and the core/peripheral circuit region 1000b. 
However, in accordance with the above-described method, the gate 90 is formed on a plane second Si epitaxial layer. As a result, a gate channel length is decreased as a design rule of the semiconductor device is reduced. Moreover, an oxide film is formed at the interface of the Si epitaxial layer and the semiconductor substrate where a storage node contact is to be formed. Accordingly, the leakage current for a storage node junction is highly depended upon an interface characteristic between the Si epitaxial layer and an oxide film. In addition, the SiGe epitaxial layer under the storage node contact is removed for forming a device isolation film. As a result, Ge in the SiGe epitaxial layer is diffused into the first Si epitaxial layer, the second Si epitaxial layer and the semiconductor substrate due to heat treatment processes prior to the formation of the device isolation film. Accordingly, the leakage current for the storage node junction is increased.